TestWay™ - Concurrent engineering

Speed new products to market by conducting test engineering activities concurrently with design activities. By using the TestWay board-level testability analyzer, test engineers can check testability, plan test strategies, predict fault coverage, and assign testpoints during the schematic design stage. The net result is fewer test problems, fewer iterations through layout, lower cost test fixture, higher test quality and faster time to market.

Concurrent engineering means slightly different things to different equipment manufacturers, but a common thread is to have some traditional test engineering functions performed during the design phase. This has seemed like a great idea since it was first proposed at least 20 years ago. Unfortunately, concurrent engineering is easier to think about and talk about than to implement effectively. The key to effective implementation is to have a software tool, such as TestWay, that enables test engineers to work from design (schematic) files efficiently and without disrupting design activities.

Check testability

Performing a manual testability review of a complex board can consume 3-5 days of a talented engineer and there is always the possibility that some problem will be overlooked. TestWay can perform an automatic testability review in a fraction of this time and with consistency that few engineers can match. Since TestWay can check testability at schematic design stage, the design can be improved.

Plan test strategies

There are many different test approaches for today’s boards. In-circuit board test, boundary scan, AOI, AXI, MDA, flying probes and perhaps others. How is a test engineer to decide on a strategy, or combination of strategies, for a particular board? TestWay enables what-if scenarios to be explored and evaluated quickly.

Predict fault coverage

TestWay quickly reports potential fault coverage based on boundary scan, in-circuit board test, cluster test or combinational test strategies. Un-testable faults are quickly identified so that the design can be modified or test points added.

Assign test points

TestWay analyzes the design (either schematic or layout) and identifies the boundary scan chains. It then determines which nets can be completely tested using boundary scan, which are partial boundary scan nets, and which are completely non-scan nets. You can direct TestWay to add more test points to obtain additional fault coverage (via clusters or direct access) on partial scan and non-scan nets. TestWay reports candidate test points to add or remove and the faults detectable as a result. This allows you to optimize fault coverage or minimize test points.

Generate tester files

TestWay can generate tester files from the schematic design files. This allows serious test development to begin before the board passes through layout.

Benefits of TestWay in Concurrent Engineering

TestWay unlocks the great potential benefits of concurrent engineering.

  • Higher test coverage by identifying testability issue while designers are still able to make modifications.
  • Higher test coverage by identifying optimal test points and back-annotating them into the schematic.
  • Fewer iterations through layout because test points can be assigned prior to layout.
  • Lower fixture costs because of fewer test points.
  • Faster time to market because many test problems can be resolved at the schematic stage.
  • Faster time to market because test programs can be substantially developed prior to layout.

A selection of our customers:

A selection of our customers
Mar 7-10


Mar 7 @ 9 h 00 min - Mar 10 @ 17 h 00 min
Nov 15-19

Electronica Munich 2022

15 Nov 2022 - 17 Nov 2022
Sep 20-22

SEPEM Toulouse 2022

20 Sep 2022 - 22 Sep 2022
May 17-20


17 May 2022 @ 9 h 00 min - 20 May 2022 @ 17 h 00 min
Jan 25-27

IPC APEX Expo 2022

25 Jan 2022 - 25 Jan 2022
San Diego
United States
Jun 9-12


9 Jun 2020 - 12 Jun 2020
Apr 29

ElectroTest Expo 2020

29 Apr 2020
Cowley, Oxford
United Kingdom