TestWay Architecture
TestWay’s electrical DfT analyzer enables designers to validate designs at the schematic capture stage, to ensure that adequate measures have been included to comply with the manufacturers test requirements. The ability to verify that PCB designs have been developed with adequate Design-for-Test in mind, is key in determining the most effective test strategies and accurately calculating fault coverage, which is crucial in improving competitive advantage, lowering cost and ensuring product quality.
How it works
The TestWay open architecture is based on a testability framework that interfaces to a variety of plug-in modules that provides both import and export opportunities, as shown below:
TestWay reads the board level netlist (schematic or layout) and model libraries. It then performs a basic topological analysis and symbolic simulation, and checks each rule, using both topological and accessibility data.
TestWay will then produce a testability report, written in a natural language that can be used by design and test engineers to validate that specific DfT criteria have been implemented.
Pour en savoir plus
Informations supplémentaires
Brochures au format PDF:
- TestWay brochure
(PDF file, 460k)
- TestWay Express brochure
(PDF file, 460k) - Coverage Testability Report (PDF file, 460k)
- The top-10 reasons you don’t design for test (PDF file, 12k)
- The powerful combination of flying probe test and JTAG test speeds up testing (PDF file, 190k)
- JTAG-centric board testing demands early design input (PDF file, 284k)
