TestWay Architecture

TestWay’s electrical DfT analyzer enables designers to validate designs at the schematic capture stage, to ensure that adequate measures have been included to comply with the manufacturers test requirements. The ability to verify that PCB designs have been developed with adequate Design-for-Test in mind, is key in determining the most effective test strategies and accurately calculating fault coverage, which is crucial in improving competitive advantage, lowering cost and ensuring product quality.

How it works


The TestWay open architecture is based on a testability framework that interfaces to a variety of plug-in modules that provides both import and export opportunities, as shown below:

TestWay topology diagramTestWay reads the board level netlist (schematic or layout) and model libraries. It then performs a basic topological analysis and symbolic simulation, and checks each rule, using both topological and accessibility data.

TestWay will then produce a testability report, written in a natural language that can be used by design and test engineers to validate that specific DfT criteria have been implemented.

Pour en savoir plus


Informations supplémentaires

Autres produits

  • QuadView, Nouvelle génération de visualisateurs
  • TPQR, Test Program Quality Report
  • Quad, Quality advisor and manager

A selection of our customers:

A selection of our customers
Nov 12-15

Productronica 2019

Nov 12 - Nov 15
Munich

Past Events

Apr 24-26

NEPCON China Shanghai 2019 – stand 1N13

Apr 24 - Apr 26
Shanghai
Chine
Mar 26

ElectroTest EXPO 2019

Mar 26
Newcastle-under-Lyme, Staffordshire
United Kingdom
Jan 26-31

IPC APEX Expo 2019

Jan 26 - Jan 31
San Diego
United States
Nov 28

SMTA Silicon Valley Expo

28 Nov 2018
San Jose, CA, USA
Nov 13-16

Electronica Munich 2018

13 Nov 2018 - 16 Nov 2018
Munich
Nov 7

PCB Carolina 2018

7 Nov 2018
NC 27606, USA