TestWay Architecture

TestWay’s electrical DfT analyzer enables designers to validate designs at the schematic capture stage, to ensure that adequate measures have been included to comply with the manufacturers test requirements. The ability to verify that PCB designs have been developed with adequate Design-for-Test in mind, is key in determining the most effective test strategies and accurately calculating fault coverage, which is crucial in improving competitive advantage, lowering cost and ensuring product quality.

How it works


The TestWay open architecture is based on a testability framework that interfaces to a variety of plug-in modules that provides both import and export opportunities, as shown below:

TestWay topology diagramTestWay reads the board level netlist (schematic or layout) and model libraries. It then performs a basic topological analysis and symbolic simulation, and checks each rule, using both topological and accessibility data.

TestWay will then produce a testability report, written in a natural language that can be used by design and test engineers to validate that specific DfT criteria have been implemented.

Pour en savoir plus


Informations supplémentaires

Autres produits

  • QuadView, Nouvelle génération de visualisateurs
  • TPQR, Test Program Quality Report
  • Quad, Quality advisor and manager

A selection of our customers:

A selection of our customers
Jun 9-12

GLOBAL INDUSTRIE 2020

Jun 9 - Jun 12
Apr 29

ElectroTest Expo 2020

Apr 29
Cowley, Oxford
United Kingdom
Mar 26

SMTA Houston Expo & Tech Forum 2020

Mar 26
Stafford, TX, USA
Mar 24

SMTA Dallas Expo & Tech Forum

Mar 24
Plano, TX, USA
Feb 4-7

IPC APEX Expo 2020

Feb 4 - Feb 5
San Diego
United States
Nov 12

Productronica 2019

12 Nov 2019
Munich
Apr 24-26

NEPCON China Shanghai 2019 – stand 1N13

24 Apr 2019 - 26 Apr 2019
Shanghai
Chine