TestWay: Design for Test and Test Coverage Analyzer

Traditionally, manufacturing and test constraints are only considered at the end of the layout phase, prior to transfer of the CAD data to production. Due to board complexity, it is now mandatory to consider a validation stage at each step of the design and manufacturing phases. TestWay has been developed to allow users to analyze each stage of the design to delivery workflow. This is achieved by the following stages:
  • Design for Component – When the key components are selected, check the ROHS, reliability, defects per million opportunities (DPMO), boundary-scan description language (BSDL) file validation in order to guide component selection.
  • Electrical Design for Test – When the schematic sheets are defined, TestWay verifies the testability by conducting electrical rules checking that reflect the Design for Test (DfT) guide lines. These can include standard and customer’s specific checks relating to company requirements.
  • Test Point Saving – By simulating the test strategy prior to the layout phase, TestWay helps to minimize the need for physical accesses that are necessary to detect defects aligned to the defect universe. It helps to reduce test point access by 30% to 70%!
  • Place the Probes – When the layout is finalized, test probe placement should be optimized according to test strategy definitions. The probe access information can then be used for estimating the test coverage, modeling the cost and calculating the production yield and TL9000 initial return rates.
  • Select manufacturing strategy – TestWay estimates test coverage using theoretical models that reflect the capabilities for a wide range of test and inspection strategies, such as: Automated Placement Machines (APM); Automatic Optical Inspection (AOI); Automated X-ray Inspection (AXI); Boundary-Scan Test (BST); Flying-probe Test (FPT); In-Circuit Test (ICT) and Functional Test These models should be tuned to reflect the test and measurement capabilities of each individual target tester.
  • Design to Build and Design to Test – TestWay exports CAD data in the native format useable by Assembly machines, Automated Optical Inspection, Automated X-Ray, In-Circuit testers, Flying probe testers and Boundary-Scan testers that is aligned to the simulated strategy. The exported files may include assembly and test programs, input lists, test models, as well as test fixture files used by the target testers. Any files created at the Design to Test stage can significantly reduce the downstream test development and fixture costs.
  • Test for Excellence – Once the test and inspection programs have been debugged and released, it is imperative to be able read the completed test program or test report and compare the coverage between the estimated and measured analysis.
  • Test for Designability – Test is an important contributor for design improvement, once a feedback loop between production and design has been established, such as a concurrent engineering approach to design and test.

Electrical Rules checking

TestWay’s electrical rules are distributed into 3 categories: Design rules, Testability rules, Boundary-scan rules. These rules are derived from formal standards and include rules commonly applied throughout the electronics industry. Specific customer requirements can be specified in a natural language using TestWay’s custom rules feature.

TestWay’s electrical rules checking validates company specific DfT requirements in real time and are easily customized to reflect updates to testability guidelines, such as:

  • Design rules to verify conformance restrictions imposed by certain technologies i.e. open-collector, bushold, specific termination requirements, noise immunity, etc.
  • In-Circuit test rules for insuring test partitioning and initialization pin control i.e. chip select, output enable, test pins etc.
  • Boundary-scan rules for verifying chain integrity, boundary-scan compliance, presence of bypass resistors, flash programming optimization, identifying boundary-scan clusters and boundary-scan bus terminations etc.
  • Custom rules to meet any specific in-house testability requirements. User may define and integrate new custom rules in real time. Then you capitalize the company technical knowledge and avoid to duplicate the same mistake twice.

Test Point Savings

With the dramatic increase in device density on PCB’s resulting in high net counts, it is virtually impossible to gain physical test access to each net for test purposes. In balancing different complementary test approaches, such as ICT, FPT and BST, TestWay optimizes the number of locations where physical test access is mandatory.

The test point optimization data can be integrated with commercial CIM layout tools to identify where physical access is required and back-annotate this information into the schematic design. In addition, TestWay provides physical confirmation that the requisite numbers of test points are placed once layout is complete.

Place the probes

Probes are placed by considering the mechanical and design for test (DfT) constraints practiced by respective companies.
Probe locations may already be defined within the CAD data, but there may be insufficient access for total test coverage. In which case the probe analyzer can be used to consider alternative top and bottom side accessibility options such as through-hole pins (THT), connectors, SMD pads, vias or bead probes etc.

Once the possible probe positions have been analyzed, the nail allocation algorithm selects the best of these opportunities for the nail positioning according to the preferences set by the user.

This allows the estimated coverage to be calculated according to the real test access.

TestWay generates a complete set of documentation:

  • Accessibility report is created to provide a list of the nodes that do not have access, with reference to the rule placement violation that prevents access.
  • Check plots and drill files.
  • List of probes and nails in MS-EXCEL format.
  • Nail retro-annotation back to the schematic. This is helpful for repair because it allows visualization of nails on the layout, schematic and virtual schematic viewers with full cross-probing.

Select manufacturing strategy

When deciding on the optimal test flow, it is important to consider all available test and inspection machines such as AOI, AXI, BST, ICT, FPT and Functional test.
The “test line” is easily defined using a simple drag and drop operation. The theoretical test models for coverage estimation and the actual test models for coverage measurement can be combined to reflect your manufacturing strategy.

The gauges provide a quick view of the level of component modeling and board accessibility. To review the respective report, you simply click-on the gauges!

Test Coverage estimation

Each of the theoretical test strategies allows selection of tester settings from a feature list for a particular test strategy.
In order to provide a more accurate estimation, any specific test features that are available on the target tester should also be included in the analysis. This aligns the estimated coverage to the real tester coverage.

TestWay handles cross optimization along the test line such as Boundary-Scan or AOI that can be used to minimize the In-Circuit Test or Flying Probe Test.

Design To Build, Design To Test

The test strategies simulation results are used to automate the assembly, test & inspection program generation for assembly machine, in-circuit test (ICT), flying-probe test (FPT), Automated X-ray Inspection (AXI), Automated Optical Inspection (AOI) and Boundary-Scan test (BST).
Output processors are available for test & inspection machines from leading suppliers such as Acculogic, Aeroflex, Agilent, Asset, Goepel Electronics, JTAG Technologies, Takaya, Teradyne/Genrad, Mydata, XJTAG and See More Output Processors
In addition to creating the test machine input files, TestWay Express also generates test models for analog multi-element components and digital models including disable configuration. Contact us for more details.

Test for Excellence: Check real coverage

The real test coverage is determined after the test has been developed and debugged, by analyzing the test program or coverage reports from a wide range of test and inspection systems used within the industry.
By analyzing the true coverage, test coverage analysis reports can be created to reflect what is actually being tested. Industry standard metrics such as PPVS (Presence, Polarity, Value, Solder), or PCOLA/SOQ (Placement, Correct, Orientation, Live, Alignment / Short, Open, Quality) are used in the coverage analysis.
We can only improve on what can be measured.
By obtaining a reference point from early coverage estimation and comparing this with the coverage provided by the real test program running on the shop floor. It is possible to identify deviations in order to drive continuous improvements.
Any test escapes (Slip) are identified and rectified prior to main stream production. Quality traceability tools used in the diagnosis and repair of printed circuit boards can take advantage of detailed test coverage analysis to improve the diagnostic resolution and speed up the repair process.


key product benefits

Ease of Use

Application wizards guide you through the project. Add multiple test strategies for project analysis, by simply drag and drop from the machine list.

Design rules checking

Confirm that specific design rules have been implemented prior to committing to PCB layout. Prevent costly design errors at the earliest possible opportunity.

DfT rules checking

Verify that DfT requirements are adhered to in order to maximize test coverage aligned to the PCB manufacturers test flow. Provide In-Circuit test rules to insure partitioning and initialization pin controllability; Boundary-Scan test rules to check Boundary Scan path integrity (JTAG), test bus control and correct termination etc.

Custom rules checking

Define and implement your own Customer’s rules rules that reflect your company or customer’s specific testability requirements.

Probe allocation & accessibility

Place probes aligned to priority rules for top or bottom side access using test points, connectors, vias, THT, SMD, bead probes, and generate detailed accessibility report.

Test coverage estimation

Maximize test and inspection coverage by estimating coverage aligned to test strategy. Perform ‘what-if’ analysis to select optimal test strategy to achieve maximum coverage based on historical DPMO data and eliminate redundant test steps. The resultant test coverage analysis can be  viewed either graphically within the viewer, or as a test coverage report (PDF file, 54k) Adobe Acrobat PDF

Functional test coverage

Manage functional test as part of the overall test strategy, produce accurate coverage reports that assist with the diagnosis of faulty boards in production and repair centers.
Eliminate redundant test steps.

Test Interface

TestWay generates input files for the following Boundary-Scan, In-Circuit & Flying-Probe testers including board description and device models.

Automated test program creation

Generate the input files for AOI, AXI, BST, ICT, FPT in a matter of minutes or hours rather than days.

Test coverage measurement

Determine the real test coverage and compare against the early estimation to identify areas for improvement.

Yield estimation

Calculate the first pass yield (FPY) by importing real time DPMO data for the manufacturing process to tune the test strategy for optimum test coverage.

Component classification

Visualize and edit component attributes such as part number, shape, class, value, tolerance, mounted status, etc.
Prompts for missing information.

Board visualization

Visualize test coverage and customer specific attributes in schematic, layout and netlist navigation views. This New-Generation Viewer also provides unique digitization feature that creates schematic view from PDF.

Cost modeling

Estimate test execution times, total engineering time and calculate hardware costs such as: test fixture frame, wiring, spring probes, vector-less sensors, etc.

Advanced reporting

Produce comprehensive reports in a variety of formats that highlight production yield, test coverage by component, estimated placement time, etc.

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Additional information

Other products

  • QuadView, Next generation viewers
  • TPQR, Test Program Quality Report
  • Quad, Quality advisor and manager

A selection of our customers:

A selection of our customers
Mar 7-10


Mar 7 @ 9 h 00 min - Mar 10 @ 17 h 00 min
Nov 15-19

Electronica Munich 2022

15 Nov 2022 - 17 Nov 2022
Sep 20-22

SEPEM Toulouse 2022

20 Sep 2022 - 22 Sep 2022
May 17-20


17 May 2022 @ 9 h 00 min - 20 May 2022 @ 17 h 00 min
Jan 25-27

IPC APEX Expo 2022

25 Jan 2022 - 25 Jan 2022
San Diego
United States
Jun 9-12


9 Jun 2020 - 12 Jun 2020
Apr 29

ElectroTest Expo 2020

29 Apr 2020
Cowley, Oxford
United Kingdom