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14-FEB-2017 to 16-FEB-2017:
APEX EXPO - ASTER Technologies are exhibiting at the APEX EXPO in San Diego between February 14th - 16th, 2017. So why not visit booth 3844 during the show, when we can discuss your requirements and demonstrate the many features of our analysis tools. (San Diego, USA)
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08-NOV-2016 to 11-NOV-2016:
ASTER announces the first system level PCB viewer integrated with National Instruments TestStand.
So why not visit the booth A1 352 when we can discuss your requirements and demonstrate our DfX & test coverage analysis tools.
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12-SEP-2016 to 15-SEP-2016:
Autotestcon - ASTER Technologies are exhibiting at Autotestcon on booth 1004 (Anaheim, USA)
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Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth 1N17 (Shanghai, China)
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15-MAR-2016 to 17-MAR-2016:
IPC APEX EXPO - Pleasevisit us at booth 1651 (Las vegas, USA)
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07-MAR-2016:
March 2016 - Newsletter n.14: Visit ASTER at IPC APEX EXPO 2016 Show in Las Vegas
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21-OCT-2015:
TestWay news 2015
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21-OCT-2015:
November 2015 - Newsletter n.12: Visit ASTER at the AUTOTESTCON 2015 Show in Maryland, USA
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10-NOV-2015 to 13-NOV-2015:
Productronica - Visit ASTER at Productronoca, Hall A1, Booth 232. Information & registration (Munich, Germany)
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IEEE AUTOTESTCON - Visit ASTER at the IEEE AutoTestCon, Booth 431. Information & registration. Press release (National Harbor, USE)
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21-APR-2015 to 23-APR-2015:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth B-1J14 (Shanghai, China)
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24-FEB-2015 to 26-FEB-2015:
IPC APEX EXPO - ASTER Technologies are exhibiting at APEX Expo between February 24th - 26th, 2015, Booth 415. So why not visit the booth during the show, when we can discuss your requirements and demonstrate the many features of our analysis tools. (San Diego, USA)
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11-NOV-2014 to 14-NOV-2014:
Electronica - ASTER Technologies are exhibiting at Electronica.
So why not visit the booth A1 352 when we can discuss your requirements and demonstrate our DfX & test coverage analysis tools. Read more …with our press release. (Munich, Germany)
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23-APR-2014 to 25-APR-2014:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth A1-1E85 (Shanghai, China)
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25-MAR-2014 to 27-MAR-2014:
IPC APEX EXPO - Booth 607 (Las vegas, USA)
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Fast Payback using TestWay

Written by Peter de Bruyn Kops - Visit Acugen on www.acugen.com

TestWay pays for itself in numerous ways. This document gives a sampling of payback avenues to help you appreciate what benefits TestWay can deliver. These paybacks cover labor savings, reduced fixturing costs, shorter time to market, higher circuit densities, accurate bidding, higher fault coverage and shorter test times.

Labor savings in testability reviews

Manual testability reviews are difficult work and require a highly skilled test engineer. For complex boards, a thorough review, done manually, can take 5 days. By using TestWay, the review can be done in one day, and most of this time is spent obtaining the right design files. At a fully loaded cost of $800 per engineering day, TestWay can save $3200 on each complex board reviewed.

Greater consistency in testability reviews

Because of the laborious nature of testability reviews and the vast amount of data to be sifted through, there is always the possibility with manual reviews that some testability problem will be missed. How often is something missed? What is the cost of missing a testability problem?

The cost of a missed testability problem can show up as lower test coverage, higher fixture cost and in many other ways. For payback calculation purposes, consider just the waste of test engineering time, both to work around the problem and sitting in meetings to see whose fault it is, who should fix it and how to prevent it happening in the future. Depending on how extensive a workaround is needed and how many people get involved in the meetings, added labor costs could easily run 4 man-days, or $3200.

Reduced fixture costs

By taking into account boundary scan virtual test points, buffer and simple logic virtual test points, and simple analog virtual test points, TestWay can reduce the number of pins required on the fixture. Assuming a typical board fixture uses 2000 of 100-mil nails ($3.50 each) and 200 of 50-mil nails ($10 each), with a nail cost of $9000, a 30% reduction in the number of nails will save $2700 per fixture.

Reduced tester costs

An important component of tester cost is the number of channels. By reducing the number of test points on boards, fewer tester channels will be required. Payback calculations are complicated by the non-linear pricing of tester channels -- they come in groups on channel cards, and after some number of cards are installed you need an additional controller or card bay. This additional controller or expansion option can be more expensive than the price of a TestWay license! If TestWay's test point optimization eliminates the need to expand your tester across one of these expensive new controller price points, TestWay pays for itself right away.

Start test development from schematic data.

Labor savings in ATE file generation

Some ATE requires laborious manual creation of various files. The most common type is device pinout models for devices used on the board. For example, Victory (Acculogic, Asset Intertech, Intellitech) needs CHAR models, Goepel needs CIC models, JTAG Technology needs a JTN netlists. TestWay can generate all these files, plus more, automatically from schematic design files. Let's assume you are a fast typist. If a new board requires 60 new models, at 10 minutes each including debug, you will spend 10 hours generating the models, or $1000 per board. With TestWay, these files are generated automatically.

Labor savings in layout

In the customary non-TestWay process, the first pass through layout assigns testpoints based on geometric criteria. Test engineers typically work on this list of test points, removing some and adding some. Adding test points requires another pass through layout which consumes the layout engineer's time. By assigning test points at the schematic stage and back annotating them into the schematic files, TestWay can save this iteration through the layout process. To calculate the magnitude of potential savings, you will need to find out how much time the layout engineer spends to put in the test engineer's manual test point additions and then multiply by $100 per hour. If TestWay saves an average of one iteration through layout, where each iteration takes a day of the layout engineer's time, then the cost savings would be $800 per board.

Time to market by saving layout steps

Using TestWay prior to layout to assign test points and back annotate them into the design files can save an iteration through layout. Since the layout engineers are presumably busy on other projects, your design may wait a while before they can get to it. This delay in layout can be on the critical path in getting the first products shipped. What is the cost of being one week late to market? If potential sales are large, or seasonal, the amount at stake with a one week delay is much larger than the cost of a TestWay license.

Time to market via concurrent engineering

Profitable, leading-edge, companies are usually the ones with a history of on-time execution of new product introductions. They are often first to market with new technology. Furthermore, new product schedules are usually not padded with lots of extra time.

In the traditional new product process flow, test engineering work begins when the board is released from physical layout. By using TestWay, test engineering work can begin prior to layout, assigning test points, determining test strategies, and even building the board-level test program on the ATE. The gating items become the fixture and first production boards. Depending on your process, potential time-to-market savings can be weeks, which makes the cost of a TestWay license look small.

Higher fault coverage

By uncovering testability issues during the design phase when they can be fixed, TestWay users obtain higher fault coverage tests. On complex boards, where the number of pins on the tester limits potential fault coverage, TestWay users obtain higher coverage by using TestWay's test point optimization features to allocate available tester pins more optimally and minimize lost coverage.

Higher fault coverage produces large savings in system test, field service and customer satisfaction, particularly for high volume products. Faults found at board test cost one tenth what they cost to find at system test. To calculate the dollar savings, you need to estimate how many boards are manufactured (e.g., 10000), the average number of faults per board before board testing (e.g., 1/10), and the cost to find a fault at system test ($1000). If TestWay allows a coverage increase from 93 to 98 percent, your payback is number of boards manufactured times number of faults per board times 5% times the cost to find a fault at system test ($50000 in this example).

Higher density, saved real estate

Some types of test points consume board real estate, perhaps by requiring a signal be especially routed to a pad on the bottom of the board. Test points have to be a minimum distance from other test points and from neighboring signal traces. While the impact of each test point is small, the space adds up. Using TestWay to eliminate 1000 or 2000 unnecessary testpoints on a complex board might make the difference between board sizes, number of layers, or even whether particular functionality will fit. What would you save by using a smaller board size or fewer routing layers? These costs depend on how many boards will be manufactured, so the savings could be significant at large volumes.

Faster flying probe tests

Flying probe tests can take a long time, with 45 minutes or more possible for complex boards. For boards containing significant boundary scan, TestWay can optimize the flying probe test to eliminate flying probe test steps on Boundary-Scan testable areas of the board. The resulting savings in flying probe test time obviously depends on the amount of boundary scan on the board, but 50% savings are possible. Assuming the fully-loaded cost of a flying probe tester is $100 per hour, savings per complex board tested can be $35,000 per thousand boards tested.

Quoting jobs, avoid the dogs

Contract test program development houses depend on accurate quoting in order to maintain profitability. All you need is one dog job in ten, with nasty testability problems that you missed in the quoting process, and your profitability disappears. Either your test engineers have to put out a heroic effort to work around the testability problems, or your sales people spend many hours in renegotiation and damage control, or both.

By using TestWay in the pre-bid analysis, these iceberg-like jobs can be priced at what they are worth, the customer's expectations set correctly, or avoided altogether. To calculate estimated payback, you need to estimate the percentage of jobs typically misbid and the cost overrun of the average misbid job. If the overrun is 5 man-days (including use of equipment), the cost penalty per misbid job would be about $4000. At one misbid job per month, payback on using TestWay would be $4000 per month.

Contractors improve competitiveness

Contract test program development is a highly competitive business. If your bid is too high, your competitor gets the order. If your bid is too low, you do not cover your costs. With TestWay to improve the consistency of your pre-bid testability reviews, your bidding accuracy will improve for complex boards and result in more profitable orders.

Competitiveness is also improved because TestWay capabilities enhance bid quality and the services you can offer your customers. For example, TestWay reports fault coverage based on the design data and your test strategy. You improve your standing with your customers by being able to set their expectations accurately regarding fault coverage of the final test program. By seeming more professional and in control of your process, you increase customers' desire to do business with you and pay a price premium.






 
     
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