A selection of our customers:
25-APR-2017 to 27-APR-2017:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth 1N14 (Shanghai, China)
14-FEB-2017 to 16-FEB-2017:
APEX EXPO - ASTER Technologies are exhibiting at the APEX EXPO in San Diego between February 14th - 16th, 2017. So why not visit booth 3844 during the show, when we can discuss your requirements and demonstrate the many features of our analysis tools. (San Diego, USA)
08-NOV-2016 to 11-NOV-2016:
ASTER announces the first system level PCB viewer integrated with National Instruments TestStand.
So why not visit the booth A1 352 when we can discuss your requirements and demonstrate our DfX & test coverage analysis tools.
12-SEP-2016 to 15-SEP-2016:
Autotestcon - ASTER Technologies are exhibiting at Autotestcon on booth 1004 (Anaheim, USA)
26-APR-2016 to 28-APR-2016:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth 1N17 (Shanghai, China)
15-MAR-2016 to 17-MAR-2016:
IPC APEX EXPO - Pleasevisit us at booth 1651 (Las vegas, USA)
March 2016 - Newsletter n.14: Visit ASTER at IPC APEX EXPO 2016 Show in Las Vegas
TestWay news 2015
November 2015 - Newsletter n.12: Visit ASTER at the AUTOTESTCON 2015 Show in Maryland, USA
10-NOV-2015 to 13-NOV-2015:
Productronica - Visit ASTER at Productronoca, Hall A1, Booth 232. Information & registration (Munich, Germany)
03-NOV-2015 to 05-NOV-2015:
IEEE AUTOTESTCON - Visit ASTER at the IEEE AutoTestCon, Booth 431. Information & registration. Press release (National Harbor, USE)
21-APR-2015 to 23-APR-2015:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth B-1J14 (Shanghai, China)
24-FEB-2015 to 26-FEB-2015:
IPC APEX EXPO - ASTER Technologies are exhibiting at APEX Expo between February 24th - 26th, 2015, Booth 415. So why not visit the booth during the show, when we can discuss your requirements and demonstrate the many features of our analysis tools. (San Diego, USA)
11-NOV-2014 to 14-NOV-2014:
Electronica - ASTER Technologies are exhibiting at Electronica.
So why not visit the booth A1 352 when we can discuss your requirements and demonstrate our DfX & test coverage analysis tools. Read more …with our press release. (Munich, Germany)
23-APR-2014 to 25-APR-2014:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth A1-1E85 (Shanghai, China)
25-MAR-2014 to 27-MAR-2014:
IPC APEX EXPO - Booth 607 (Las vegas, USA)
TestWay™ - Concurrent engineering
Speed new products to market by conducting test engineering activities concurrently with
design activities. By using the TestWay board-level testability analyzer, test
engineers can check testability, plan test strategies, predict fault
coverage, and assign testpoints during the schematic design stage. The net
result is fewer test problems, fewer iterations through layout, lower cost
test fixture, higher test quality and faster time to market.
Concurrent engineering means slightly different things to different equipment
manufacturers, but a common thread is to have some traditional test
engineering functions performed during the design phase. This has seemed
like a great idea since it was first proposed at least 20 years ago.
Unfortunately, concurrent engineering is easier to think about and talk
about than to implement effectively. The key to effective implementation is
to have a software tool, such as TestWay, that enables test engineers to
work from design (schematic) files efficiently and without disrupting design
Performing a manual testability review of a complex board can consume 3-5 days
of a talented engineer and there is always the possibility that some problem
will be overlooked. TestWay can perform an automatic testability review in a
fraction of this time and with consistency that few engineers can match. Since
TestWay can check testability at schematic design stage, the design can be
Plan test strategies
There are many different test approaches for today's boards. In-circuit board
test, boundary scan, AOI, AXI, MDA, flying probes and perhaps others. How is a
test engineer to decide on a strategy, or combination of strategies, for a
particular board? TestWay enables what-if scenarios to be explored and evaluated
Predict fault coverage
TestWay quickly reports potential fault coverage based on boundary scan,
in-circuit board test, cluster test or combinational test strategies. Un-testable
faults are quickly identified so that the design can be modified or test points
Assign test points
TestWay analyzes the design (either schematic or layout) and identifies the
boundary scan chains. It then determines which nets can be completely tested
using boundary scan, which are partial boundary scan nets, and which are
completely non-scan nets. You can direct TestWay to add more test points to
obtain additional fault coverage (via clusters or direct access) on partial scan
and non-scan nets. TestWay reports candidate test points to add or remove and
the faults detectable as a result. This allows you to optimize fault coverage or
minimize test points.
Generate tester files
TestWay can generate tester files from the schematic design files. This allows
serious test development to begin before the board passes through layout.
Benefits of TestWay in Concurrent Engineering
TestWay unlocks the great potential benefits of concurrent engineering.
- Higher test coverage by identifying testability issue while designers
are still able to make modifications.
- Higher test coverage by identifying optimal test points and
back-annotating them into the schematic.
- Fewer iterations through layout because test points can be assigned
prior to layout.
- Lower fixture costs because of fewer test points.
- Faster time to market because many test problems can be resolved at the
- Faster time to market because test programs can be substantially
developed prior to layout.