A selection of our customers:

ASTER's satisfied customers

Latest news:

25-APR-2017 to 27-APR-2017:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth 1N14 (Shanghai, China)

14-FEB-2017 to 16-FEB-2017:
APEX EXPO - ASTER Technologies are exhibiting at the APEX EXPO in San Diego between February 14th - 16th, 2017. So why not visit booth 3844 during the show, when we can discuss your requirements and demonstrate the many features of our analysis tools. (San Diego, USA)

08-NOV-2016 to 11-NOV-2016:
ASTER announces the first system level PCB viewer integrated with National Instruments TestStand.
So why not visit the booth A1 352 when we can discuss your requirements and demonstrate our DfX & test coverage analysis tools.

12-SEP-2016 to 15-SEP-2016:
Autotestcon - ASTER Technologies are exhibiting at Autotestcon on booth 1004 (Anaheim, USA)

26-APR-2016 to 28-APR-2016:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth 1N17 (Shanghai, China)

15-MAR-2016 to 17-MAR-2016:
IPC APEX EXPO - Pleasevisit us at booth 1651 (Las vegas, USA)

March 2016 - Newsletter n.14: Visit ASTER at IPC APEX EXPO 2016 Show in Las Vegas
TestWay news 2015
November 2015 - Newsletter n.12: Visit ASTER at the AUTOTESTCON 2015 Show in Maryland, USA
10-NOV-2015 to 13-NOV-2015:
Productronica - Visit ASTER at Productronoca, Hall A1, Booth 232. Information & registration (Munich, Germany)

03-NOV-2015 to 05-NOV-2015:
IEEE AUTOTESTCON - Visit ASTER at the IEEE AutoTestCon, Booth 431. Information & registration. Press release (National Harbor, USE)

21-APR-2015 to 23-APR-2015:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth B-1J14 (Shanghai, China)

24-FEB-2015 to 26-FEB-2015:
IPC APEX EXPO - ASTER Technologies are exhibiting at APEX Expo between February 24th - 26th, 2015, Booth 415. So why not visit the booth during the show, when we can discuss your requirements and demonstrate the many features of our analysis tools. (San Diego, USA)

11-NOV-2014 to 14-NOV-2014:
Electronica - ASTER Technologies are exhibiting at Electronica.
So why not visit the booth A1 352 when we can discuss your requirements and demonstrate our DfX & test coverage analysis tools. Read more …with our press release. (Munich, Germany)

23-APR-2014 to 25-APR-2014:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth A1-1E85 (Shanghai, China)

25-MAR-2014 to 27-MAR-2014:
IPC APEX EXPO - Booth 607 (Las vegas, USA)

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TestWay: Electrical DfT & Fault Coverage Analyzer

TestWay’s electrical DfT analyzer enables designers to validate designs at the schematic capture stage, to ensure that adequate measures have been included to comply with the manufacturers test requirements. The ability to verify that PCB designs have been developed with adequate Design-for-Test in mind, is key in determining the most effective test strategies and accurately calculating fault coverage, which is crucial in improving competitive advantage, lowering cost and ensuring product quality.

Download Now TestWay Brochure
TestWay Brochure 

How it works

The TestWay open architecture is based on a testability framework that interfaces to a variety of plug-in modules that provides both import and export opportunities, as shown below:

TestWay reads the board level netlist (schematic or layout) and model libraries. It then performs a basic topological analysis and symbolic simulation, and checks each rule, using both topological and accessibility data.

TestWay will then produce a testability report, written in a natural language that can be used by design and test engineers to validate that specific DfT criteria have been implemented.
TestWay topology diagram

Key product benefits

Design rules checking

Verify that specific design rules have been adhered to prior to committing to PCB layout. Prevent costly design errors at the earliest possible opportunity.

DfT rules checking

Verify that DfT requirements are adhered to in order to maximize test coverage aligned to the PCB manufacturers test flow. Provide In-Circuit test rules to insure partitioning and initialization pin controllability; Boundary-Scan test rules to check Boundary Scan path integrity (JTAG), test bus control and correct termination etc.

Custom rules checking

Define and implement your own Customer’s rules rules that reflect your company or customer's specific testability requirements.

Test point saving

Identify nets not requiring physical test access and only place test points where absolutely necessary. TestWay balances the different test approaches provided by AOI, AXI, BST, FT, FPT, ICT etc, and optimizes the number of mandatory test accesses, resulting in fewer test probes and significantly reduces test fixturing costs due to less complex fixtures.

Test coverage estimation

Maximize test and inspection coverage by estimating coverage aligned to test strategy. Perform ‘what-if’ analysis to select optimal test strategy to achieve maximum coverage based on historical DPMO data and eliminate redundant test steps. The resultant test coverage analysis can be  viewed either graphically within the viewer, or as a test coverage report (PDF file, 54k) Adobe Acrobat PDF 

Test coverage measurement

Determine real test efficiency against theoretical coverage and identify areas for improvement. By reading real test programs or coverage reports, TestWay controls real test efficiency against estimated coverage, identifying uncovered areas and any redundant tests.

Functional test coverage

Manage functional test as part of the overall test strategy, produce accurate coverage reports that assists the diagnosis of faulty boards in production and repair centers.

Test Interface

TestWay generates input files for the following Boundary-Scan, In-Circuit & Flying-Probe testers including board description and device models.

Board visualization

Visualize test coverage and customer specific attributes in schematic, layout and netlist navigation views. This New-Generation Viewer also provides unique digitization feature that creates schematic view from PDF.

Advanced reporting

Produce comprehensive reports in a variety of formats that highlight predicted production yield, test coverage by component type, predict placement time, etc.

Cost modeling

Predict test execution times, total engineering time and calculate hardware costs such as; test fixture, power supply, spring probes, wiring and vector-less sensors etc.

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Additional information

Other products

  • QuadView, Next generation viewers
  • TPQR, Test Program Quality Report
  • Quad, Quality advisor and manager
  • QuadFeederSafe, make your feeder settings secure
  • WildScan, Boundary-Scan test translation

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