A selection of our customers:
25-APR-2017 to 27-APR-2017:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth 1N14 (Shanghai, China)
14-FEB-2017 to 16-FEB-2017:
APEX EXPO - ASTER Technologies are exhibiting at the APEX EXPO in San Diego between February 14th - 16th, 2017. So why not visit booth 3844 during the show, when we can discuss your requirements and demonstrate the many features of our analysis tools. (San Diego, USA)
08-NOV-2016 to 11-NOV-2016:
ASTER announces the first system level PCB viewer integrated with National Instruments TestStand.
So why not visit the booth A1 352 when we can discuss your requirements and demonstrate our DfX & test coverage analysis tools.
12-SEP-2016 to 15-SEP-2016:
Autotestcon - ASTER Technologies are exhibiting at Autotestcon on booth 1004 (Anaheim, USA)
26-APR-2016 to 28-APR-2016:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth 1N17 (Shanghai, China)
15-MAR-2016 to 17-MAR-2016:
IPC APEX EXPO - Pleasevisit us at booth 1651 (Las vegas, USA)
March 2016 - Newsletter n.14: Visit ASTER at IPC APEX EXPO 2016 Show in Las Vegas
TestWay news 2015
November 2015 - Newsletter n.12: Visit ASTER at the AUTOTESTCON 2015 Show in Maryland, USA
10-NOV-2015 to 13-NOV-2015:
Productronica - Visit ASTER at Productronoca, Hall A1, Booth 232. Information & registration (Munich, Germany)
03-NOV-2015 to 05-NOV-2015:
IEEE AUTOTESTCON - Visit ASTER at the IEEE AutoTestCon, Booth 431. Information & registration. Press release (National Harbor, USE)
21-APR-2015 to 23-APR-2015:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth B-1J14 (Shanghai, China)
24-FEB-2015 to 26-FEB-2015:
IPC APEX EXPO - ASTER Technologies are exhibiting at APEX Expo between February 24th - 26th, 2015, Booth 415. So why not visit the booth during the show, when we can discuss your requirements and demonstrate the many features of our analysis tools. (San Diego, USA)
11-NOV-2014 to 14-NOV-2014:
Electronica - ASTER Technologies are exhibiting at Electronica.
So why not visit the booth A1 352 when we can discuss your requirements and demonstrate our DfX & test coverage analysis tools. Read more …with our press release. (Munich, Germany)
23-APR-2014 to 25-APR-2014:
Nepcon CHINA - Vist ASTER during NEPCON exibition on Booth A1-1E85 (Shanghai, China)
25-MAR-2014 to 27-MAR-2014:
IPC APEX EXPO - Booth 607 (Las vegas, USA)
TestWay™ - Test Point Savers
For PC Board using through-hole technology, it is used to get a full physical
accessibility with one test access per net. Testability was maximal:
commandability, observability, test efficiency and troubleshooting tasks were
With the drastically increase in term of density report most of the time this
interesting configuration is no longer true and leads to the following
conclusion: It is more and more difficult to reach all of the nets for any test
For most of the test strategies, this lack of access directly leads to fault
coverage lost and of course to test efficiency lost.
To face this problem, two complementary approaches have been developed:
- To improve test interface design in order to get fine pitch bed of nails
- Reduce the number of required test points to get a good test coverage
(measure of test efficiency)
In most of the design cycle strategies, test accesses are chosen after the
layout phase. It is performed according to classic constraints such as connector
pads, via diameter, isolation... For a given net, when no test access can be
defined according to those constraints, this net is classify as inaccessible.
For today’s PC Boards, this way of choosing test accesses without any
relationship to the fault coverage, only using geometrical criteria is at least
strange and not adequate with the testing challenge the electronic industry have
To provide an alternative and better solution to test accesses choice,
TestWay provides a full and structured
approach from schematic capture to layout:
In a traditional design cycle, TestWay allows to analyze what should be the
consequences of a lost of physical accessibility for the global test efficiency.
By considering existing test accesses, TestWay determines the test coverage
(nets and devices that is not tested or with a low efficiency) and proposes
additional test points in order to get a significant increase of test
- Test efficiency analysis according to test accesses identified at the
layout stage or declared at the schematic capture.
- Proposal to reduce the number of test points necessary to get a good
- Proposal to increase test efficiency by adding a limited number of test
- Clusters identification: Defining devices groups to be tested together
using a reduced number of accesses.
In a concurrent engineering design cycle, TestWay identifies soon during the
schematic capture just the necessary test points to get after the layout phase
the desire accessibility for a good test efficiency.
Reduce the number of accesses
According to the fact that one test access per net is no longer possible to
obtain only a virtual access may allow to keep an acceptable fault coverage.
Fig. 1: Coverage = f(Physical or virtual access)
A virtual access is available each time it is possible to affect a logic state
by propagation in an up stream chain (commandability) and to get a
measurement result by propagation in a down stream chain (observability).
Fig. 2: Virtual access
Up and down stream chains must be designed so that signal propagation is easy.
According to this, 1149.1 Boundary-Scan standard test strategy provides a
virtual access to each of the device pins.
Interconnect Test Analysis
A net is testable when it is possible to affect a logic state through a first
channel and to get a measurement result by a second one.
Several configurations may take place:
TestWay-ITA (Interconnect Test Analyzer) module performs nets classification
in order to affect to each of them a priority level for test access allocation.
- Output state generation through a device, measurement through a tester
- State generation through the JTAG chain, measurement through a tester
- State generation through a tester channel, measurement through the JTAG
- State generation through the JTAG chain measurement from an other cell
in the JTAG chain.
Fig. 3: Interconnect Test Analysis
Surrounding nets analyze allows to classify each net in one of the
following nine groups:
To adjust the analyze, each group is split in sub groups each with a
predefined priority level for test access allocation. TestWay identifies
unnecessary test points and provides also suggestion about what should
be modify in the design to reduce the number of necessary test accesses.
- Ground nets
- Power nets
- Unused pins
- Pins only connected to a pull resistor
- Boundary-Scan testability bus
- PURE Boundary-Scan nets
- PARTIAL Boundary-Scan nets
- Tester access
- Non-scan nets with no tester access
Device Test Analysis
TestWay-DTA module is intended to verify according to the overall test
accesses available that it is possible to apply a logic state on each device
inputs and to measure the resulting states at least on one output.
If it is possible to drive all of the inputs the theoretical test
efficiency may be given by the following formula:
DTA module then proposes to try to increase the test fault coverage by adding
a limited number of new test accesses. Adding a test access allows to
increase up stream device observability and down stream devices
commandability. Greatest priority is given to commandability increase which
will have as a secondary effect observability increases too.
A better commandability allows to drive much more devices and a better
observability leads to a higher fault coverage with a higher diagnostic
Report presents steps for maximizing the number of testable devices using the
minimum number of additional test points. The way of working is the
following: "If you add N physical accesses, you will test M devices more".
This process is implemented until an optimum test coverage is reached.
DTA module identify clusters in partitioning the board in independent
A cluster is often a group of non-JTAG devices whose inputs and outputs are
coming from accessible points.
Cluster borders identification leads to interconnection file automatic
generation which contains cluster description and its primary accesses. If a
cluster is composed of programmable devices, RAM, PROM memories or low
complexity devices, test vectors and fault dictionary generation should be done
automatically using adequate existing tools.
- Cluster is a device block which will be tested together at the same time
with the same vectors using a limited number of test accesses.
- Internal net accesses to this kind of block is not so much important to
obtain a good fault coverage. Fault dictionary use allows to keep a high
level of default localization.
- Device type analysis is an important parameter to define easy testable
- Boundary-Scan clusters have this particular characteristic to have some
of their access points connected to partial boundary scan nets.
PC Board fault coverage
Using fault coverage computed by ITA and DTA,
TestWay shows the test efficiency of the
overall PC Board using colors on electrical diagram. This feature allows the
users to quickly identify how adding supplementary test access or removing
existing test points may improve the test coverage of its PC Board.